Seniconductor memory device with capacitor

ABSTRACT

The invention includes a process for the fabrication of semiconductor device, comprising the steps of forming a trench in the interlayer of semiconductor substrate, depositing impurities doped a amorphous silicon served as a lower electrode all over the trench, forming a resist so as to expose the top portion of the amorphous silicon in the trench, etching the amorphous silicon layer except for the trench, implanting impurities into the top portion of the amorphous silicon and growing HSG silicon by means of heat treatment after resist strip.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to a semiconductor memory and a method offabricating the same, and more particularly, to a capacitor of asemiconductor memory device having a hemispherical grained (HSG) layerand a method of fabricating the same.

[0003] 2. Description of Related Art

[0004] A conventional forming method of a semiconductor memory device isexplained in the following manner. A trench 2 is formed in a siliconsubstrate 1 and this trench is filled with a CVD oxide. The trench 2 isplanarized by chemical mechanical polishing (CMP) technique, so that atrench isolation region 2 is formed (see FIG. 1A).

[0005] Thereafter, a layer of thin oxide 3 is grown on all the surfacesby thermal oxidation. Layers of polycrystalline silicon 4 and tungsten 5are next deposited by CVD, and etched in order to define gate electrodes6 of MOS transistors and interconnects 7 (see FIG. 1B).

[0006] Next, a layer of interoxide 8 is deposited by CVD, and etched todefine a bitline contact hole 9 in the layer of interoxide 8. Layers ofpolysilicon 10 and tungsten silicide are deposited on all the surfaces,and etched to form a bitline 12 (see FIG. 1C).

[0007] Moreover, layers of interoxide 13 silicon nitride 14 arerespectively deposited by CVD. Cell contact holes 15 are defined both inlayers interoxide 13 and silicon nitride 14 by etching. A layer ofpolycrystalline silicon 16 heavily doped impurities is deposited on allthe surfaces, and is polished by CMP method. Only the contact holes 15are filled with the polycrystalline silicon 16 (see FIG. 2A).

[0008] A layer of a thick insulator 17 is deposited by CVD, and holesare opened in the insulator 17 by etching to form lower electrodes. Alayer of a amorphous silicon 18, which is doped phosphorous of 0.5E20 to3E20 cm−3, is deposited by CVD, and only the opening holes are filledwith resists 19(see FIG. 2B).

[0009] Next, after all the surfaces are etched, the insulators 17 areremoved by hydrogen fluoride solution, resulting that cylindrical lowerelectrodes 20 are formed (see FIG. 2C).

[0010] Heat treatment is carried out in a silane gas ambient under lowpressure, and hemispherical grains (HSGs) are grown on the surface ofthe amorphous silicon 18, so that lower electrodes 20 of cylindricalcapacitors have rough surfaces (see FIG. 3A).

[0011] A layer of thin silicon nitride 21 is deposited on the lowerelectrodes 20 by CVD, and a layer of polycrystalline silicon dopedimpurities is deposited on the silicon nitride 21. As a result, a memorycell, which is composed of a cylindrical capacitor over the MOStransistors 3, have been completed (see FIG. 3B).

[0012] However, in the above-described conventional capacitor structure,there are some problems, as is described below. Stress is caused on alower electrode surface of a cylindrical capacitor because of anucleation of a polycrystalline silicon HSG, when a HSG rough surface isformed. The stress is centralized on the top of the cylindricalcapacitor, where the grain of HSG closes together. It results that thegrains on the top on the lower electrode of the capacitor are peel offand cause a short failure between neighboring capacitors.

SUMMARY OF THE INVENTION

[0013] In order to solve these problems, the present invention isprovided, wherein a semiconductor memory device, which has a capacitorcomprising of both the first electrode located outside of the capacitorand next to the neighboring capacitor and having grain silicon grownfrom amorphous silicon layer, and the second electrode formed on asemiconductor substrate, in which grain size at the top portion of thefirst electrode is smaller than the other portions of the firstelectrode. Also, in the present invention, the impurity concentration atthe top portion of the amorphous silicon is higher than the otherportions.

[0014] According to the present invention, there is provided a method offabricating a semiconductor device, including forming a trench in theinterlayer of semiconductor substrate, depositing impurities doped aamorphous silicon served as a lower electrode all over the trench,forming a resist so as to expose the top portion of the amorphoussilicon in the trench, etching the amorphous silicon layer except forthe trench, implanting impurities into the top portion of the amorphoussilicon and growing HSG silicon by means of heat treatment after resiststrip.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIGS. 1A to 1C are sectional views for explaining a conventionalmethod for forming a capacitor electrode.

[0016]FIGS. 2A to 2C are sectional views for explaining a conventionalmethod for forming a capacitor electrode subsequent to FIG. 1C.

[0017]FIGS. 3A to 3C are sectional views for explaining a conventionalmethod for forming a capacitor electrode subsequent to FIG. 2C.

[0018]FIGS. 4A to 4C are sectional views for explaining a method forforming a capacitor electrode according to the present invention.

[0019]FIG. 5 is a graph showing a failure chip dependent on phosphorousconcentration at the top of a lower electrode.

DETAILED DESCRIPTION OF THE INVENTION

[0020] Referring to FIG. 4, after the same processes as the conventionalthrough FIG. 2B to FIG. 1 are performed, a layer of resist 102 is buriedinside a layer of amorphous silicon 101, and a upper portion of thelayer of the amorphous silicon 101 is exposed, as is shown in FIG. 4A.

[0021] Next, phosphorous ions are implanted at about 5 to 15 KeV. Also,arsenic can be implanted instead of phosphorous. The implantation iscarried out only at the top portion 104 of the amorphous silicon layer101, because only the top portion of the amorphous silicon layer 101 isexposed.

[0022] At this time, phosphorous ions of 0.5E20 to 3.0E20 cm−3 havealready been doped the layer of the amorphous silicon 101, so thatphosphorous concentration of the top portion 104 of the amorphoussilicon layer 101 becomes higher than the other portions.

[0023] Thereafter, heat treatment is carried out in a silane gas ambientunder vacuum condition as same as the conventional method, and grainsize of the amorphous silicon layer 101 becomes larger. It results thatthe grain grows into a hemispherical grain (HSG) and the lower electrode105 of the capacitor has a HSG rough surface.

[0024] Moreover, a cylindrical capacitor is formed by using theconventional method.

[0025] In the present embodiment, the grain growth rate at the topportion of the lower electrode 104 is larger than at the other portionsand it is difficult to form HSG, because phosphorous concentration ofthe top portion is higher than the other portions.

[0026]FIG. 5 shows a result that a short failure between neighboringcylindrical capacitors is checked electrically. In FIG. 5, the graphshows failure chip versus phosphorous concentration of the top portion.The graph shows that the failure chip rapidly decrease with increase ofthe phosphorous concentration and saturates at the concentration ofabove 3E20 cm−3.

[0027] For example, when the amorphous silicon layer 101 has alreadybeen doped phosphorous ions of 1E20 cm−3, a net concentration is above3E20 cm−3 at the top portion if ion implantation is carried out at above2E20 cm−3 dose.

[0028] As described above in detail, in the manufacturing steps of thepresent invention, the top portion of a amorphous silicon layer is dopedphosphorous prior to a HSG growth of the amorphous silicon layer whichserves as a lower electrode, wherein the phosphorous concentration ofthe amorphous silicon layer becomes higher than the other portions. Itresults that HSG growth is suppressed at the top portion of theamorphous silicon layer. So that the HSG silicon of the top portion doesnot peel off and failures of electrical short do not occur even ifstress is caused during the HSG growth or in the step followed by theHSG growth. Therefore, it is possible to realize highly reliablecapacitor.

What is claimed is:
 1. A capacitor of a memory cell formed on a siliconsubstrate, said capacitor comprising: A first electrode and secondelectrode, said first electrode disposing opposite to said secondelectrode and adjacent to the neighboring capacitor; Said firstelectrode having HSG roughness grown from amorphous silicon on itssurface, the HSG roughness of the top portion of said first electrodebeing smaller than the other portions of said first electrode.
 2. Thecapacitor of the claim 1, wherein said first electrode disposes outsidesaid capacitor and said second electrode disposes inside said capacitor;3. The capacitor of the claim 1, wherein said first electrode is madefrom amorphous silicon;
 4. The capacitor of the claim 3, whereinimpurity concentration at the top portion of said first electrode ishigher than that at the other portion of said first electrode;
 5. Thecapacitor of the claim 4, wherein said impurity is either phosphorous orarsenic.
 6. The capacitor of the claim 4, wherein impurity concentrationat the top portion of said first electrode is more than 3E20 cm−3;
 7. Amethod of fabricating a memory device, said method comprising thefollowing steps: forming a first insulating layer on a semiconductorsubstrate; forming a trench in said first insulating layer; forming anamorphous silicon layer doped impurities on the all surface; forming aresist film in said trench filled with said amorphous silicon so as toexpose a upper portion of said amorphous layer; etching all the surfaceso as to leave said amorphous silicon in said trench; implantingimpurity ions into said top portion of said amorphous silicon; makingsaid amorphous silicon grow with HSG surface by heat treatment afterremoving said resist film.
 8. The method of the claim 7, wherein saidimpurity is phosphorous or arsenic.
 9. The method of the claim 7,wherein impurity concentration of said top portion of said amorphoussilicon is more than 3E20 cm−3.
 10. The method of the claim 8, whereinimpurity concentration of said top portion of said amorphous silicon ismore than 3E20 cm−3.